module CSSTE(
    input         clk_100mhz,
    input         RSTN,
    input  [3:0]  BTN_y,
    input  [15:0] SW,
    output [3:0]  Blue,
    output [3:0]  Green,
    output [3:0]  Red,
    output        HSYNC,
    output        VSYNC,
    output [15:0] LED_out,
    output [7:0] AN,
    output [7:0] segment
);


	wire rst;
	wire [3:0] BTN_OK;
	wire [15:0] SW_OK;
	wire [31:0] clk_div;
	wire Clk_CPU;
	wire [31:0] inst_in;
	wire [31:0] Data_in;
	wire MemRW;
	wire [31:0] PC;
	wire [31:0] Data_out;
	wire [31:0] Addr_out;
	wire [31:0] dmem_i_data;
	wire [31:0] dmem_o_data;
	wire clk_n;
	wire data_ram_we;
	wire [9:0] ram_addr;
	wire [15:0] led_out;
	wire [31:0] counter_out;
	wire counter0_out;
	wire counter1_out;
	wire counter2_out;
	wire GPIOf0000000_we;
	wire GPIOe0000000_we;
	wire counter_we;
	wire [31:0] P_Data;
	wire clk_cpu_n;
	wire [1:0] counter_set;
	wire [7:0] point_out;
	wire [7:0] LE_out;
	wire [31:0] Disp_num;
	
	assign clk_n=~clk_100mhz;
	assign clk_cpu_n=~Clk_CPU;
	assign LED_out=led_out;
	
	SAnti_jitter U9(
	.clk(clk_100mhz),
  	.RSTN(RSTN),
  	.Key_y(BTN_y),
  	.SW(SW),
  	.BTN_OK(BTN_OK),
  	.SW_OK(SW_OK),
  	.rst(rst)
  	);
  	
  	clk_div U8(
  	.clk(clk_100mhz),
  	.rst(rst),
	.SW2(SW_OK[2]),
 	.SW8(SW_OK[8]),
  	.STEP(SW_OK[10]),
  	.clkdiv(clk_div),
  	.Clk_CPU(Clk_CPU)
  	);
	
	SCPU U1(
	.clk(Clk_CPU),
	.rst(rst),
  	.inst_in(inst_in),
  	.Data_in(Data_in),
	.MemRW(MemRW),
	.PC_out(PC),
	.Data_out(Data_out),
	.Addr_out(Addr_out)
 	);	
	
	ROM_B U2 (
  	.a(PC[11:2]),      // input wire [9 : 0] a
  	.spo(inst_in)  // output wire [31 : 0] spo
	);
	
	RAM_B U3 (
  	.clka(clk_n),    // input wire clka
  	.wea(data_ram_we),      // input wire [0 : 0] wea
  	.addra(ram_addr),  // input wire [9 : 0] addra
  	.dina(dmem_i_data),    // input wire [31 : 0] dina
  	.douta(dmem_o_data)  // output wire [31 : 0] douta
	);
	
	MIO_BUS U4(
	.clk(clk_100mhz),
 	.rst(rst),
  	.BTN(BTN_OK),
  	.SW(SW_OK),
 	.mem_w(MemRW),
 	.Cpu_data2bus(Data_out),
 	.addr_bus(Addr_out),
 	.ram_data_out(dmem_o_data),
 	.led_out(led_out),
 	.counter_out(counter_out),
 	.counter0_out(counter0_out),
  	.counter1_out(counter1_out),
 	.counter2_out(counter2_out),
 	.Cpu_data4bus(Data_in),
  	.ram_data_in(dmem_i_data),
  	.ram_addr(ram_addr),
  	.data_ram_we(data_ram_we),
  	.GPIOf0000000_we(GPIOf0000000_we),
  	.GPIOe0000000_we(GPIOe0000000_we),
  	.counter_we(counter_we),
  	.Peripheral_in(P_Data)
  	);
	
	Multi_8CH32 U5(
	.clk(clk_cpu_n),
  	.rst(rst),
	.EN(GPIOe0000000_we),
	.Test(SW_OK[7:5]),
	.point_in({clk_div[31:0],clk_div[31:0]}),
	.LES(64'b0),
	.Data0(P_Data),
	.data1({2'b0,PC[31:2]}),
	.data2(inst_in),
	.data3(counter_out),
	.data4(Addr_out),
	.data5(Data_out),
	.data6(Data_in),
	.data7(PC),
	.point_out(point_out),
  	.LE_out(LE_out),
  	.Disp_num(Disp_num)
  	);
  	
  	Seg7_Dev_0 U6 (
  	.disp_num(Disp_num),  // input wire [31 : 0] disp_num
  	.point(point_out),        // input wire [7 : 0] point
  	.les(LE_out),            // input wire [7 : 0] les
  	.scan(clk_div[18:16]),          // input wire [2 : 0] scan
  	.AN(AN),              // output wire [7 : 0] AN
  	.segment(segment)    // output wire [7 : 0] segment
	);
	
	SPIO U7(
 	.clk(clk_cpu_n),
  	.rst(rst),
	.Start(clk_div[20]),
	.EN(GPIOf0000000_we),
	.P_Data(P_Data),
	.counter_set(counter_set),
	.LED_out(led_out)
	);
	
	
	Counter_x U10(
	.clk(clk_cpu_n),
  	.rst(rst),
  	.clk0(clk_div[6]),
  	.clk1(clk_div[9]),
  	.clk2(clk_div[11]),
  	.counter_we(counter_we),
  	.counter_val(P_Data),
  	.counter_ch(counter_set),
 	.counter0_OUT(counter0_out),
 	.counter1_OUT(counter1_out),
  	.counter2_OUT(counter2_out),
  	.counter_out(counter_out)
  	);
	
	
	VGA U11(
	.clk_25m(clk_div[1]),
    .clk_100m(clk_100mhz),
    .rst(rst),
    .pc(PC),
    .inst(inst_in),
    .alu_res(Addr_out),
    .mem_wen(MemRW),
    .dmem_o_data(dmem_o_data),
    .dmem_i_data(dmem_i_data),
    .dmem_addr(Addr_out),
    .hs(HSYNC),
    .vs(VSYNC),
    .vga_r(Red),
    .vga_g(Green),
    .vga_b(Blue)
    );

endmodule